document number: 91134 www.vishay.com s10-2463-rev. c, 08-nov-10 1 power mosfet IRFD320, sihfd320 vishay siliconix features ? dynamic dv/dt rating ? repetitive avalanche rated ? for automatic insertion ?end stackable ?fast switching ? ease of paralleling ? simple drive requirements ? compliant to rohs directive 2002/95/ec description third generation power mosfets from vishay provide the designer with the best combi nation of fast switching, ruggedized device design , low on-resistance and cost-effectiveness. the 4 pin dip package is a low cost machine-insertiable case style whic h can be stacked in mu ltiple combinations on standard 0.1" pin centers. th e dual drain serveres as a thermal link to the mounting surface for power dissipation levels up to 1 w. notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. v dd = 50 v, starting t j = 25 c, l = 21 mh, r g = 25 ? , i as = 2.0 a (see fig. 12). c. i sd ? 2.0 a, di/dt ? 40 a/s, v dd ? v ds , t j ? 150 c. d. 1.6 mm from case. product summary v ds (v) 400 r ds(on) ( ? )v gs = 10 v 1.8 q g (max.) (nc) 20 q gs (nc) 3.3 q gd (nc) 11 configuration single n-channel mosfet g d s hvmdip d s g rohs compliant ordering information package hvmdip lead (pb)-free IRFD320pbf sihfd320-e3 snpb IRFD320 sihfd320 absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 400 v gate-source voltage v gs 20 continuous drain current v gs at 10 v t a = 25 c i d 0.49 a t a = 100 c 0.31 pulsed drain current a i dm 3.9 linear derating factor 0.0083 w/c single pulse avalanche energy b e as 48 mj avalanche current a i ar 0.49 a repetitive avalanche energy a e ar 0.10 mj maximum power dissipation t a = 25 c p d 1.0 w peak diode recovery dv/dt c dv/dt 4.0 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (p eak temperature) for 10 s 300 d * pb containing terminations are not rohs compliant, exemptions may apply
www.vishay.com document number: 91134 2 s10-2463-rev. c, 08-nov-10 IRFD320, sihfd320 vishay siliconix notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. pulse width ? 300 s; duty cycle ? 2 %. thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient r thja - 120 c/w specifications (t j = 25 c, unless otherwise noted) parameter symbol test condi tions min. typ. max. unit static drain-source brea kdown voltage v ds v gs = 0 v, i d = 250 a 400 - - v v ds temperature coefficient ? v ds /t j reference to 25 c, i d = 1 ma - 0.51 - v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 2.0 - 4.0 v gate-source leakage i gss v gs = 20 v - - 100 na zero gate voltage drain current i dss v ds = 400 v, v gs = 0 v - - 25 a v ds = 320 v, v gs = 0 v, t j = 125 c - - 250 drain-source on-state resistance r ds(on) v gs = 10 v i d = 0.21 a b --1.8 ? forward transconductance g fs v ds = 50 v, i d = 1.2 a 1.7 - - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz, see fig. 5 - 410 - pf output capacitance c oss - 120 - reverse transfer capacitance c rss -47- total gate charge q g v gs = 10 v i d = 2.0 a, v ds = 320 v, see fig. 6 and 13 b --20 nc gate-source charge q gs --3.3 gate-drain charge q gd --11 turn-on delay time t d(on) v dd = 200 v, i d = 3.3 a, r g = 18 ? , r d = 56 ? , see fig. 10 b -10- ns rise time t r -14- turn-off delay time t d(off) -30- fall time t f -13- internal drain inductance l d between lead, 6 mm (0.25") from package and center of die contact -4.0- nh internal source inductance l s -6.0- drain-source body diode characteristics continuous source-dr ain diode current i s mosfet symbol showing the integral reverse p - n junction diode - - 0.49 a pulsed diode forward current a i sm --3.9 body diode voltage v sd t j = 25 c, i s = 0.49 a, v gs = 0 v b --1.6v body diode reverse recovery time t rr t j = 25 c, i f = 3.3 a, di/dt = 100 a/s b - 270 600 ns body diode reverse recovery charge q rr -1.43.0c forward turn-on time t on intrinsic turn-on time is negligible (turn-on is dominated by l s and l d ) d s g s d g
document number: 91134 www.vishay.com s10-2463-rev. c, 08-nov-10 3 IRFD320, sihfd320 vishay siliconix typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics, t a = 25 c fig. 2 - typical output characteristics, t a = 150 c fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature t a = 25 c t a = 150 c
www.vishay.com document number: 91134 4 s10-2463-rev. c, 08-nov-10 IRFD320, sihfd320 vishay siliconix fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area t a = 25 c t j = 150 c s in g le pul s e
document number: 91134 www.vishay.com s10-2463-rev. c, 08-nov-10 5 IRFD320, sihfd320 vishay siliconix fig. 9 - maximum drain curre nt vs. ambient temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-ambient i d , drain current (a) t a , ambient temperature (c) pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f thermal re s pon s e (z thja ) t 1 , rectangular pul s e duration ( s )
www.vishay.com document number: 91134 6 s10-2463-rev. c, 08-nov-10 IRFD320, sihfd320 vishay siliconix fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate charge test circuit r g i as 0.01 w t p d.u.t. l v ds + - v dd 10 v var y t p to obtain required i as i as v ds v dd v ds t p q gs q gd q g v g charge 10 v d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + -
document number: 91134 www.vishay.com s10-2463-rev. c, 08-nov-10 7 IRFD320, sihfd320 vishay siliconix fig. 14 - for n-channel vishay siliconix maintains worldw ide manufacturing capability. prod ucts may be manufactured at on e of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents su ch as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91134 . p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage rever s e recovery current body diode forward current v gs = 10 v a i s d driver gate drive d.u.t. l s d waveform d.u.t. v d s waveform inductor current d = p.w. period + - + + + - - - peak dio d e recovery d v/ d t test circuit v dd ? dv/dt controlled by r g ? driver s ame type a s d.u.t. ? i s d controlled by duty factor d ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low s tray inductance ? g round plane ? low leakage inductance current tran s former r g note a. v gs = 5 v for logic level device s v dd
document number: 91361 www.vishay.com revision: 06-sep-10 1 package information vishay siliconix hvm dip (high voltage) note 1. package length does not include mold flash, protrusions or gate burrs. package width does not include interlead flash or prot rusions. inches millimeters dim. min. max. min. max. a 0.310 0.330 7.87 8.38 e 0.300 0.425 7.62 10.79 l 0.270 0.290 6.86 7.36 ecn: x10-0386-rev. b, 06-sep-10 dwg: 5974 0.248 [6.29] 0.240 [6.10] 0.197 [5.00] 0.189 [4.80] 0.024 [0.60] 0.020 [0.51] 0.160 [4.06] 0.140 [3.56] 0.180 [4.57] 0.160 [4.06] 4 x 0.100 [2.54] typ. a l 0.045 [1.14] 0.035 [0.89] 2 x 0.043 [1.09] 0.035 [0.89] 0.094 [2.38] 0.086 [2.18] 0.017 [0.43] 0.013 [0.33] 0 to 15 2 x e min. e max. 0.133 [3.37] 0.125 [3.18]
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